The present application relates to oscillator circuits, and more particularly to low-power, low-phase noise clock signal generators.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventive scope, and are not necessarily admitted to be prior art.
A variety of approaches exist for generating electronic device clock signals, with varying types of limitations. For example, quartz crystal oscillators may be useful for frequencies under about 200 MHz, and can provide highly stable frequency outputs with very little phase noise, but can be sensitive to temperature and vibration and may face size or frequency limitations. LC oscillators connected to a divider, as well as MEMS (micro-electromechanical systems) oscillators such as bulk acoustic wave (BAW) resonators, can also be used to produce situationally useful clocks. However, divider circuits are generally power-hungry because of transitions at the oscillator frequency, and MEMS oscillators at relatively low frequencies (e.g., 200 MHz to 1 GHz) may be too large to fit within a device area budget.
FIG. 2A shows an example of a locking range graph 200 of an oscillator. For an oscillator operating at a particular base frequency ω0 202, the range of amplitudes and frequencies of a signal injected into which will cause the oscillator to injection lock (explained below) is called the oscillator's “locking range” 204. When a first oscillator is disturbed by a second oscillator operating at a nearby frequency, and the coupling is strong enough and the frequencies near enough, the second oscillator can “capture” the first oscillator, causing the first oscillator to oscillate at an approximately identical frequency to the second oscillator. This is injection locking. That is, for first and second oscillators with different operating frequencies, there is a minimum amplitude of the second oscillator signal that will cause the first oscillator to injection lock to the second oscillator's operating frequency. Beneath that minimum amplitude, there is a region 206 where the first oscillator will not lock. The minimum amplitude for injection locking is primarily determined by the operating frequencies of the first and second oscillators, the difference between those frequencies, and the respective structures of the oscillators. While the second oscillator's signal continues to be injected into the first oscillator at a sufficient amplitude, the first oscillator will continue to output a signal at (approximately) the operating frequency of the second oscillator. See, e.g., FIG. 5 regarding injection locking, and particularly regarding the time-dependent sensitivity of an oscillator to an injected signal.
Injection locking can also occur when the first oscillator is operating at a frequency nearby a harmonic of the second oscillator's operating frequency; or when a harmonic of the first oscillator's operating frequency is nearby the second oscillator's operating frequency; or when a harmonic of the first oscillator's operating frequency is near a harmonic of the second oscillator's operating frequency.
Output of an oscillator can be input back into the oscillator to induce self-injection locking. Self-injection locking induced on an oscillator by a sufficiently group-delayed oscillator output signal can result in significantly lowering the phase noise in the self-injection locked oscillator output signal.
FIG. 2B schematically shows an example of a self-injection locking phase locked loop 208 (SILPLL). See L. Zhang, A. Daryoush, A. Poddar and U. Rohde, “Oscillator phase noise reduction using self-injection locked and phase locked loop (SILPLL),” 2014 IEEE International Frequency Control Symposium (FCS), Taipei, 2014, pp. 1-4, which is incorporated herein by reference. As shown, an SILPLL 208 comprises a voltage controlled oscillator 210 (VCO), a self-phase locked loop 212 (SPLL), a 1 km to 3 km optical fiber cable 214 used to introduce a group delay so that injection locking will reduce phase noise in the VCO 210 output, and a self-injection locking (SIL) block 216 that injects the group-delayed VCO 210 output back into the VCO 210, connected in looped series. The output of the VCO 210 comprises the output of the SILPLL 208 (through a 10 dB coupler), as well as being fed back to the SPLL 212. (MZM stands for Mach-Zehnder modulator.) Phase noise improvement in an SILPLL 208 as shown is proportional to the delay time introduced by the optical fiber 214. As a result of the length of the optical fiber 214 required to achieve phase noise improvement, there is a floor on the device area required by an SILPLL 208 as shown that achieves significant phase noise reductions in the VCO 210 output.
FIG. 2C schematically shows an example of a self-injection-locking oscillator 218. See Heng-Chia Chang, “Stability analysis of self-injection-locked oscillators,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 9, pp. 1989-1993, September 2003; and Heng-Chia Chang, “Phase noise in self-injection-locked oscillators—theory and experiment,” in IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 9, pp. 1994-1999, September 2003; both of which are incorporated herein by reference. An output signal 220 from an oscillator 222 is directed by a circulator 224 to a delay line, high Q resonator, or amplifier 226 (for example, a microwave resonant cavity measuring approximately five to six cm in length and containing a standing wave) tuned to the same frequency as the oscillator 222. (The pictured power divider and spectrum analyzer are not relevant here.) The group-delayed output 228 of the delay line, high Q resonator, or amplifier 226 is then directed by the circulator 224 back to the oscillator 222. The group-delayed output 228 is then injected into the oscillator 222 so that the oscillator 222 locks to its own, group-delayed output signal 228.
Injection locking can also be used with a ring oscillator to provide frequency division. FIG. 2D shows an example of a transistor-level diagram of a divide-by-three injection locked frequency divider 230 (ILFD). See X. Yi, C. C. Boon, M. A. Do, K. S. Yeo and W. M. Lim, “Design of Ring-Oscillator-Based Injection-Locked Frequency Dividers With Single-Phase Inputs,” IEEE Microwave and Wireless Components Letters, vol. 21, no. 10, pp. 559-561, October 2011, which is incorporated herein by reference. The circuit shown in FIG. 2C is based on a 3-stage ring oscillator 232.
As shown in FIG. 2D, an input signal RF is connected through a capacitor and an inductor (Bias Tee) to an Injection Circuit node Vinj. Vinj biases the gates of three transistors M1, M2 and M3, which are connected source to drain M3 to M2 to M1 to M3. The source of M1 is connected to node V1, the source of M2 is connected to node V2, and the source of M3 is connected to node V3. Cp,1, Cp,2 and Cp,3 are parasitic capacitances of nodes V1, V2 and V3, respectively. A transistor 234 has its source connected to VDD, its drain connected to node V1, and is biased by oscillator 232 input voltage Vb. Vb is a control voltage for the ring oscillator 232; Vb controls the frequency of the ring oscillator 232 by increasing or decreasing the current available to each stage through corresponding PMOS transistors 234, 238, 242. A transistor 236 has its source connected to ground, its drain connected to node V1, and its bias connected to node V3 and the source of M3. A transistor 238 has its source connected to VDD, its drain connected to node V2, and is biased by oscillator 232 input voltage Vb. A transistor 240 has its source connected to ground, its drain connected to node V2, and its bias connected to node V1. A transistor 242 has its source connected to VDD, its drain connected to node V3, and is biased by oscillator 232 input voltage Vb. A transistor 244 has its source connected to ground, its drain connected to node V3, and its bias connected to node V2. A transistor 246 has its source connected to ground, its drain connected to oscillator output OUT, and its bias connected to node V3 and the source of M3.
Given the preceding, NMOS transistor 236 is a first amplifier, with its gate driven by PMOS transistor 242 drain voltage V3, and having an output at node V1. NMOS transistor 240 is a second amplifier, with its gate driven by PMOS transistor 234 drain voltage V1, and having an output at node V2. NMOS transistor 244 is a third amplifier, with its gate driven by PMOS transistor 238 drain voltage V2, and having an output at node V3. Node V3 drives the gate of transistor 246 so as to provide the oscillator output shown as OUT, and node V3 is fed back to drive the gate of NMOS transistor 236 (the first amplifier) as described. Thus, the first, second and third amplifiers are effectively connected in a “ring” structure with the sequential complementary connectors creating an oscillating signal.
Generally, in 3-stage ring oscillators, there is a one third phase delay between each stage (from V1 to V2, from V2 to V3, and from V3 to V1). As shown in FIG. 2D, the injection signal Vinj is injected (at M1, M2 and M3) such that it affects all three stages (V1, V2, V3). (Vinj, V1, V2 and V3 are also used to refer to respective nodes in the ILFD 230.) The ILFD 230 as designed acts as a frequency divider with a division ratio of three (3). The injection signal Vinj therefore causes the oscillator 232 to lock to a frequency that is one third of the frequency of the injection signal Vinj.
The inventors endeavor to disclose new and advantageous approaches to producing low-power, low-phase noise periodic oscillator signals (e.g., electronic device clock signals), as further described below.